The subject matter disclosed herein generally relates to DC offset cancellation devices.
FIG. 1 depicts a conventional wide band amplifier that includes a DC offset cancellation circuit 100 and voltage amplifier 105. DC offset cancellation circuit 100 may include transconductive amplifier 102-B and input termination resistors 110. Voltage amplifier 105 may include a transconductive amplifier 102-A and loads 120.
Input return loss measures how much power loss occurs for an increment of incident power. An input return loss value is defined mathematically as xe2x88x9220*log10(S11), where S11 represents a ratio of (a) power reflected from input terminals to (b) power incident to such input terminals. The DC offset cancellation circuit 100 of FIG. 1 may have an S11 value represented by the following relationship:
(Zinxe2x88x92R)/(Zin+R), where
Zin is the input impedance of the DC offset cancellation circuit 100 (as measured from terminal INPUT), and
R is the resistance of a single ended resistor 110 measured with respect to AC ground.
The input impedance, Zin, may be equivalent to a single resistor 110 in parallel with an input capacitance of amplifier 102-A and in parallel output capacitance of amplifier 102-B. As the frequency of an input signal to terminal INPUT increases, the input impedance, Zin, decreases. Consequently, input return loss may increase with increasing frequency. Therefore, DC offset cancellation circuit 100 may have an undesirable impact on input return loss performance for high frequency input signals.